1. Technical Field of the Invention
The present invention relates to memories in integrated circuits of the SRAM type and, more particularly, to reading memory cells of the above type.
2. Description of Related Art
FIG. 1 schematically illustrates a memory plan MEM, which conventionally comprises word lines WLi and columns COLj, wherein each column includes two bit lines BLT and BLF.
The memory cells of such a memory plan, illustrated in detail in FIG. 2, are connected differentially between two bit lines BLT and BLF of each column of the memory plan and can be activated by a word line WLi. Further, reading amplifiers (sense amplifiers) SA are placed at the foot (end) of the columns of the memory plan and are classically activated by an activation signal Act (sense amp enable).
A base memory cell CELL of the memory plan is illustrated in FIG. 2. It comprises a locking (latch) circuit formed by a first inverter IA and a second inverter IB cross-connected between a first node A and a second node B. Each inverter thus has its output connected to the input of the other inverter. A first access transistor TA is provided, whereof a drain is connected to the node A, whereof a gate is connected to a word line WL of the memory plan and whereof a source is connected to a first bit line BLT. A second access transistor TB is likewise provided whereof a drain is connected to the node B, whereof a gate is connected to a word line WL and whereof a source is connected to the second bit line BLF of the column of the memory cell.
A reading operation of such a memory cell usually comprises a precharge phase of the bit lines to which the memory cell is connected.
More precisely, during the precharge phase, the two bit lines BLT and BLF are first precharged to a reading potential corresponding classically to the nominal supply voltage Vdd of the device and the corresponding word line WL is then subjected to the potential Vdd (WL=1 logic) to select the memory cell in reading. Then, the two bit lines BLT and BLF are made floating. Since the word line WL is at the high potential Vdd, the n-channel access transistors TA and TB of the cell are thus made in the on-state.
In an example where the node A of the memory cell selected in reading is at logic 0 and where the node B is thus at logic 1, with the line BLT being precharged at the potential Vdd, the two sides of the channel of the access transistor TA are at different potentials, such that a current Iread circulates through this channel. This current Iread will discharge the line BLT and thus progressively bring its potential to 0 volts (logic 0). However, as the node B of the memory cell and the bit line BLF are at the same potential Vdd, the two sides of the channel of the transistor TBO are at the same potential and no current circulates in this channel. The line BLF is thus supposed to remain in its high state of precharge, i.e. at potential Vdd.
After a certain period, the amplifier SA detects a difference in potential between the lines BLT and BLF, which, when greater than the input offset voltage of the amplifier, produces a data signal at the output of the amplifier corresponding to the data stored in the memory cell controlled in reading.
Associated classically with such a reading operation performed on a memory cell is an operating margin, known as the Static Noise Margin (SNM). In the same way, an operating margin, known as the Write Margin, is linked to an operation for writing a memory cell. These margins, for reading or writing, reflect the capacity of a memory cell to be read or written without being perturbed. They are antagonists, meaning to the extent where improvement made to one is done to the detriment of the other.
Currently all circuits are focusing on lowering the size of memories. And yet, the drop in the size of the components causes substantial electrical variability of transistors, which negatively influences the margins for reading and writing of a memory cell by augmenting their dispersion. This degradation phenomenon of the margins for reading and writing is further accentuated by the decrease in supply voltages used in the circuits. In other words, novel technologies are employed, which concomitantly aim for an increasingly smaller circuit size and the use of increasingly lower supply voltages, make reading and writing operations increasingly difficult by lowering the available margins.
So, with low margins, at the moment of reading a memory cell, when the word line is activated to select the memory cell in reading, the locking circuit of the memory cell holding the data can be perturbed by the precharge voltage of the bit lines BLT and BLF, which typically correspond to the nominal supply voltage Vdd.
In reference to FIG. 3, illustrating the value of the margin at the SNM reading as a function of the precharge voltage of the bit lines VBL, it is evident that precharge of the bit lines at the supply voltage Vdd, for example 1.2 volts, does not produce an optimal margin value at the reading.
Even though correct for the majority of the memory cells of the memory plan, the SNM margin value corresponding to a precharge at Vdd of the bit lines can, however, prove inadequate to ensure reading without perturbation of the most restricting cells of the memory plan (especially those having local deviations—such as mismatch or non-matching).
There is a need to eliminate these drawbacks by proposing a memory device of SRAM type, in which the SNM parameter defining the margin at reading a memory cell is improved, such that reading a memory cell is favored.